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HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 1
A. General Description --
HT-6560B is a VL_Bus Enhanced IDE Controller which provides a control logic and data path between 486, 386 VL_Bus and IDE drives. The HT-6560B is fully compatible with the ANSI ATA revision 4a specification for IDE hard disk operation and VESA VL_Bus revision 1.0 specification for local bus PC drives. The HT-6560B is a high performance and fully design for IDE application. At the host CPU interface, HT-6560B provides a posted write and pre-fetched read fully 32 bits data path. It can operate up to 50 MHz and zero wait-state cycle. Double word read and write operations are provided. It also allows concurrent IDE and CPU memory operations to maximize system performance. Flexible IDE drive interface timing selection. Power on reset latch the adequate IDE active and recovery time into configuration register. HT-6560B also allows you to detect IDE performance and change the configuration register by software program.
B. Features --
* * * * * * * * * * * * * * *
Pin-to-pin backward compatible with HT-6560A VL_Bus IDE controller IDE interface to 486 and 386 DX/SX local bus VESA VL_Bus rev 1.0 compatible Connects directly to VL_Bus and IDE interface, no extra TTL needed Supports 16 bits and 32 bits data transfer Supports pipeline pre-fetched data reads and posted writes for concurrent disk and host operations Supports 4 layer R/W FIFO (32 bits x 4) Supports two IDE channels, up to 4 IDE drivers Supports ATAPI CD ROM and TAPE DRIVER protocal Direct interface to all hard disk drives that are ANSI ATA compatible Program mable command active and cycle time Supports IOCHRDY in PIO mode Supports mode 3, mode 4 PIO data transfer 100-pin PQFP package Software driver supported
HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 2
C. Block Diagram --
F ig.1
D. Pin Assignment --
HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 3
E. Pin Description --
Pin No. Pin Name I/O Description Secondary drive chip select 3 is normally an active low output pin to select the control block registers in the drive. During power on reset, this is an input pin to set DIORN/DIOWN cycle time and sampled on the rising edge of RSTN. This signal is negated to extend the host transfer cycle of any host command or data register access when the drive is not ready to respond to a data transfer request. When IORDY is not negated, IOCHRDY is in a high impedance state. +5V POWER. GROUND. Drive I/O read is an active low output which enables data to be read from the drive. The duration and repetition rate of DIORN cycles is determined by the type of IDE drive and programmed by HT-6560B. Drive I/O write is an active low output which enables data to be written to the drive. The duration and repetition rate of DIOWN cycles is determined by the type of IDE drive and programmed by HT-6560B. Ready return is an active low signal which indicates the end of the current host CUP transfer. Address strobe is an active low input signal which indicates that there is a valid address and command on the bus. Write (active high) or read (active low) is an input which distinguishes between write and read cycles. Memory (active high) or I/O (active low) is an input which distinguished between momory and I/O cycles.
1
CS37XN
I/O
2
IORDY
I
3,28,53,78 4,15,29,40,54, 65,79,90
VDD VSS
-- --
5
DIORN
O
6
DIOWN
O
7
RDYRTNN
I
8
ADSN
I
9
WRN
I
10
MION
I
HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 4
Pin No. 11
Pin Name DCN
I/O I
Description Data (active high) or control (active low) is an input which is used to distinguish between I/O and interrupt or halt cycles. Primary or secondary I/O port selection input. Level low for primary, level high for secondary I/O port. Disk change is an input which comes from floopy diskette drive connector pin 34. P rim a r y d rive ch ip select 1 is active lo w o u tp u t p in to select the com m a nd block registers in the drive. P rim a r y d r ive ch ip select 3 is no rm a l a n active low output pin to select the control block registers in the drive. During power on r e se t, th is is an inp ut pin to se t DIORN/DIOWN cycle time and sampled on the rising edge of RSTN. Drive address, bit 2 is an output to the IDE connector for register selection in the drive. Drive address, bit 1 is an output pin to the IDE connector for register selection in the drive. Drive address, bit 0 is an output pin to the IDE connector for register selection in the drive. These are the host address bits 2 through 9 from the host address bus. No connection pins. Local device is an active low output which indicates that the current host CPU com mand cycle is a valid HT-6560B address.
12
S0
I
13
DSKCHGN
I
14
CS1FXN
I/O
16
CS3FXN
I/O
17 18 19 20~27 30~35 36
DA2 DA1 DA0 LA2~LA9 NC LDEVN
I/O I/O I/O I -- O
37
LRDYN
Local ready is an active low output which indicates that the current host CPU transfer Tri-O h a s c o m p le te d . A s th e c u rr e n t c y c le is completed, the LRDYN will immediately pull low and remain active for one T-state.
HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 5
Pin No.
Pin Name
I/O
Description Host data is the 32 bits bi-directional data bus w h ic h c o n n e cts to th e h ost C P U LD [7 :0 ] define the lowest data byte while LD[31:24] define the m ost significant data byte. The active bytes on a CPU transfer are specified b y th e B E N [3 :0 ] s ig n a ls . T h e L D b u s is normally in high impedance state and is driven only after T2 state of HT-6560B read cycles. VL_Bus clock. Drive data bus, bits 15 through 0, are the 16 bits bi-directional data bus which connects to the IDE drive. DD[7:0] define the lowest data byte while DD[15:8] define the most significant data byte. System reset is an active low input. Byte enable bits 0 through 3 from the host CPU address bus. These inputs are active low and specify which bytes will be valid for host read/write data transfers. ID E e na ble is an active high input w hich enable the HT-6560B for drive operation. Low input which disables HT-6560B. Secondary drive chip select 1 is normally an active low output pin to select the control block registers in the drive. During power on r e se t, th is is an inp ut p in for te st an d sampled on the rising edge of RSTN.
38,39,46,48~52, 58~60,62~64, LD31~LD0 71~76,83,85~89 ,91,93~96,98
I/O
41
CLK
I
42~44,47,55,56, 61,69,70,77,81, DD15~DD0 82,84,92,97,99 45 RSTN
I/O
I
57,66~68
BEN3~0
I
80
IDEEN
I
100
CS17XN
I/O
HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 6
F. Absolute Maximum Ratings --
Parameter Supply Voltage Input/Output Voltage Storage Temperature Temperature Under Bias Plastic Plastic Symbol V DD V I ,V O T STG T BIAS Minimum -0.5 V SS -0.5 -40 -40 Maximum 6 V DD +0.5 125 85 Unit V V
C C
G. Recommended Operating Conditions --
Parameter Supply Voltage Input High Voltage for Normal Input Input Low Voltage for Normal Input Operating Temperature Symbol V DD V IH V IL TA Min. 4.75 2.2 -- 0 Typ. 5.0 -- -- 25 Max. 5.25 -- 0.8 70 Unit V V V
C
H. DC Characteristics --
Symbol I DDS V OH1 Parameter Power Supply Current Output High Voltage for Normal Output (LD[31:0]) Output High Voltage for Driver Output (DD[15:0], DA[2:0], CS1FXN, CS3FXN, CS17XN, CS37XN, DIORN, DIOWN, LDEVN, LRDYN) Output Low Voltage for Normal Output (LD[31:0]) Output Low Voltage for Driver Output (DD[15:0], DA[2:0], CS1FXN, CS3FXN, CS17XN, CS337XN, DIORN, DIOWN, LDEVN, LRDYN) Input Pull-Up Resistor Input Pull-Down Resistor Condition Steady state. I OH =2.5mA Min. -- Typ. -- 4.5 Max. 0.2 Unit mA V
V OH2
I OH =4.5mA
4.5
V
V OL1
I OL =8mA
0.5
V
V OL2
I OL =11mA
0.5
V
RP RN
440K 255K

HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 7
I. Functional Description --
The HT-6560B contains seven major blocks as shown in fig.1. They are state control unit, address decoder, read ahead buffer (read FIFO), read ahead counter, posted write buffer (write FIFO), FIFO counter and configuration register. The state control unit contains a state machine which controls all of the read/write timing and data swapping between CPU and IDE drives. The address decoder connects to VL_Bus directly, decodes valid address of the HT- 6560B configuration register and IDE drive registers. Read ahead buffer (or read FIFO) and posted write buffer (or write FIFO) which can accelerate the data read/write speed. User can set the command active and recovery time to optimize the IDE performance by programming the configuration register. In addition to, you can detect and set primary or secordary IDE port through the configuration register.
1. Restet Initialization Siganl Name CS1FXN CS3FXN CS17XN CS37XN LDEVN DIOWN DIORN LRDYN DA[2:0] LD[31:0] DD[15:0] 1 Hight-Impedance Hight-Impedance Hight-Impedance 1 1 1 High-Impedance 1 High-Impedance High-Impedance Signal State During Reset
HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 8
2. Host Interface a. CPU cycle definition: MION 0 0 0 0 1 1 1 1 DCN 1 1 0 0 0 0 1 1 WRN 0 1 0 1 0 1 0 1 Address Space 1F0h-1F7h and 3F6h-3F7h for primary drive. 170h-177h and 376h-377h for secondary drive. IDE Cycle DIORN CYCLE
1F0h-1F7h and 3F6h-3F7h for primary drive. DIOWN 170h-177h and 376h-377h for secondary drive. CYCLE Don't care. Don't care. Don't care. Don't care. Don't care. Don't care. NOP NOP NOP NOP NOP NOP
b. HT-6560B write data operation: CPU Write Byte Enable BEN3 0 0 1 1 1 1 BEN2 0 1 0 1 1 1 BEN1 0 1 1 0 0 1 BEN0 0 1 1 0 1 0 HT-6560A Input Data LD[31:24] LD[23:16] LD[15:8] valid valid X X X X valid X valid X X X valid X X valid valid X LD[7:0] valid X X valid X vaild
HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 9
c. HT-6560B read data operation: CPU Read Byte Enable BEN3 0 0 1 1 1 1 BEN2 0 1 0 1 1 1 BEN1 0 1 1 0 0 1 BEN0 0 1 1 0 1 0 LD[31:24] valid valid same as LD[23:16] HT-6560B Output Data LD[23:16] valid same as LD[31:24] valid LD[15:8] valid same as LD[31:24] same as LD[23:16] LD[7:0] valid same as LD[31:24] same as LD[23:16]
same as LD[15:0] same as LD[15:8] same as LD[7:0] same as LD[15:8] same as LD[7:0] valid
valid same as LD[15:8] valid
same as LD[7:0]
3. IDE Interface a. DA[2:0] generation: LA2 0 0 0 0 1 1 1 1 BEN[3:0] XX00 XX01 X011 0111 XXX0 XX01 X011 0111 DA[2:0] 000 001 010 011 100 101 110 111
b. Drive select signal operation: Signal Name CS1FXN CS3FXN CS17XN CS37XN Address Range 1F0h-1F7h for primary drive. 3F6h-3F7h for primary drive. 170h-177h for secondary drive. 376h-377h for secondary drive.
HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 10
J. HT-6560B Register Setting --
1. Active Time and Recovery Time Setting a. Hardware setting: There are four kind of cycle times that you can select during power on reset. CS3FXN 0 1 0 1 CS37XN 0 0 1 1 ACTIVE (Cycles) 15 10 7 4 RECOVERY (Cycles) 15 10 7 4
b. Software setting: After power on reset, you still can program the configuration register by following procedures:
* *
Read I/O port 3E6h four times to turn on configuration mode. Wrtie 8 bits data to I/O prot 1F6h for primary port or 176h for secondary port.
Recovery time: Data bit7 0 0 bit6 0 0
bit5 1 1
bit4 0 1
Cycles 2 3
1 0 Active time: Data bit3 0 0
1 0
1 0
1 0
15 16
bit2 0 0
bit1 1 1
bit0 0 1
Cycles 2 3
1
1
1
1
15
*
Read I/O port 1F7h for primary port or 177h for secondary port one time to clear configuration mode.
HT -- 6560B
VL_BUS ENHANCED IDE CONTROLLER
DEC.07.1994 PAGE: 11
2. Primary and Secondary I/O Port Setting a. Hardware setting: During power on reset, this register can be latched from the S0 pin. S0 0 1 I/O Port 1F0~7h, 3F6~7h, 3E6h (primary) 170~7h, 376~7h, 3E6h (secondary)
b. Software setting: After power on reset, you can program the I/O port register by writing port 3E6h. bit 0 0 1 I/O Port 1F0~7h, 3F6~7h, 3E6h (primary) 170~7h, 376~7h, 3E6h (secondary)
This bit also can be read in data bit0 from port 3E6h. 3. Register 3E6h: bit 0: PSPORT Primary and secondary I/O port setting bit 1: reserved bit 2: FIFOEN This enable FIFO function bit 3: reserved bit 4: reserved bit 5: PFTCH This enable pre-fetched data read function
DD[0..15]
VCC
VCC
C S 1 7 DL DL L L L DL XDDDDDDDDD N1 0 4 0 0 0 0 3 0 1234 5 50 L L L L L DL DD DDDDDDDDD 000012111 67890 143
S3 LD01 LD03 IORDY VCC DIORN DIOWN CS37XN IORDY 12 C S 1 7 X N IDEEN L L DL VL L L L L DL DD DDDDSDDDDDDDDD 3 4 3 5 S6 7 8 9 1 2 1 1 1 0 143
C1 0.1uf J1
19999999999888888888 09876543210987654321 0 U1
LD00 LD02 LD04 LD06 LD08 LD05 LD07 LD09 LD11 LD13 LD15 LD17
LD10 LD12
LD14 LD16 LD18 LD20 LD19 LD21 LD23 LD25 DSKCHGZ LD27 LD29 LD31 DA2 DA1 DA0
DIORN DIOWN RDYRTN ADSN WRN MION DCN S0 DSKCHGZ CS1FXN
K. Application Circuit --
LD22 LD24 LD26 LD28 LD30
HT-6560B/C
DD1 LD12 LD13 LD14 LD15 LD16 LD17 DD0 DD12 BEN2 BEN1 BEN0
CS3FXN DA2 DA1 DA0 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 LD18 LD19 LD20 DD7 LD21 LD22 LD23 BEN3 DD11 DD10 DMACKN L R D Y N L D 3 1 R L DVCDDDS 3 SL DDDT 0 SK5 8 9 N LL L DDDD 2 D2 2 9687 L D 2 6 LD24 LD25
VCC
LA[2..15]
LA[2..9] LA08 LA06 LA04 VCC BEN0 BEN1 BEN2 C4 10U IRQ14 IRQ15 R1 10K BEN3 ADSN DHHI I L MI I R R D A RRQQE RQQ1 1 V Q1 2 4 5 N LLL RDD D3 3 Y1 0 N
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 IDEEN VSS VDD DD1 LD12 LD13 LD14 LD15 LD16 LD17 DD0 DD12 BEN2 BEN1 BEN0 VSS LD18 LD19 LD20 DD7 LD21 LD22 LD23 BEN3 DD11 DD10 VSS VDD LD24 LD25
DL DL L DDDDD CS37XN 10412 IORDY 5 VDD VSS DIORN DIOWN RDYRTNN ADSN WRN MION DCN S0 DSKCHGN CS1FXN VSS CS3FXN DA2 DA1 DA0 LA2 LA3 LA4 LA5 LA6 LA7 LA8 LA9 DHHI I L VDD MI I R R D VSS DMACKN A R R Q Q E RQQ1 1 V Q1 2 4 5 N 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 33333333344444444445 12345678901234567890
LA09 LA07 LA05
LA03 LA02
L DDDRL DL L L CDDDEDDDDD L 5 8 9 S2 6 2 2 2 K E9 876 T N
RESETN
RESETN DCN MION WRN
59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 DAT00 DAT02 DAT04 DAT06 DAT08 GND DAT10 DAT12 VDC DAT14 DAT16 DAT18 DAT20 GND DAT22 DAT24 DAT26 DAT28 DAT30 VDC ADR31 GND ADR29 ADR27 ADR25 ADR23 ADR21 ADR19 GND ADR17 ADR15 VDC ADR13 ADR11 ADR09 ADR07 ADR05 GND ADR03 ADR02 N/C RESET# D/C# M/IO# W/R# DAT01 DAT03 GND DAT05 DAT07 DAT09 DAT11 DAT13 DAT15 GND DAT17 VDC DAT19 DAT21 DAT23 DAT25 GND DAT27 DAT29 DAT31 ADR30 ADR28 ADR26 GND ADR24 ADR22 VDC AD20 ADR18 ADR16 ADR14 ADR12 ADR10 ADR08 GND ADR06 ADR04 WBACK# BE0# VDC BE1# BE2# GND BE3# ADS#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
RDYRTN
PAD1
HT -- 6560B
LCLK
106 107 108 109 110 111 112 113 114 115 116 RDYRTN# GND IRQ9 BRDY# BLAST# ID0 ID1 GND LCLK VDC LBS16# PAD2 VL-BUS CON LRDY# LDEV# LREQ# GND LGNT# VDC ID2 ID3 ID4 LKEN# LEADS#
48 49 50 51 52 53 54 55 56 57 58
PAD1&PAD2 Short: For HT-6560B Open : For HT-6560C
DD[0..15] IDE1 RESETN RESETN
DD[0..15] IDE2
VCC R9 22K J2 123 R11 4.7K CS3FXN
VL_BUS ENHANCED IDE CONTROLLER
RESETN DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
RESETN DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15
R10 22K
J3 123
R12 4.7K CS37XN DIOWN DIORN IORDY
PAGE:
DIOWN DIORN IORDY
J6 DA1 DA0 CS1FXN
VCC
12
R2
DMARQ DIOWN DIORN IORDY DMACKN HIRQ1 DA1 DA0 CS1FXN DA2 CS3FXN
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DA2 CS3FXN
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
DA1 DA0 CS17XN
DMARQ DIOWN DIORN IORDY DMACKN HIRQ2 DA1 DA0 CS17XN
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
DA2 CS37XN
DA2 CS37XN
DEC.07.1994
330
12

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